EXYNOS4412時鐘管理單元譯文
時間：2018-09-29 來源：未知
This chapter describes the Clock Management Units (CMUs) of Exynos 4412 SCP. CMUs control Phase Locked Loops (PLLs) and generate system clocks for CPU, buses, and function clocks for inpidual IPs in Exynos 4412 SCP. They also communicate with the power management unit (PMU) in order to stop clocks before entering certain low power mode to reduce power consumption by minimizing clock toggling.
本章節描述了Exynos4412片上系統的時鐘管理單元（CMUs）。CMUs控制鎖相環（PLLs）產生系統時鐘，供CPU、總線和Exynos4412片上系統的個別設備端口（IPs）來使用。當進入低電壓模式前需要停止時鐘以小化時鐘切換帶來的電源損耗的時候，時鐘管理單元（CMUs）會同電源管理單元（PMU）交互。
7.1 Clock Domains。時鐘域
In Exynos 4412 SCP, it clocks the function blocks asynchronously with each other to provide a wider choice of operating frequencies. It also eases physical implementation.
在Exynos4412片上系統中，它為各個功能塊之間的異步通信提供一個寬泛的操作頻率區間。它還能消除各個功能塊的時鐘物理硬件的實現。
1） CPU block consists of the Cortex-A9 MPCore processor, L2 cache controller, and CoreSight. It operates at voltage levels of 0.875 V ~ 1.30 V. The Cortex-A9 MPCore operates at 200 MHz ~ 1.4 GHz and CoreSight Clock is up to 200MHz. The CMU in CPU block (CMU_CPU) generates all the necessary clocks for IPs in CPU block. It also generates certain control signals for Cortex-A9 MPCore.
CPU塊由Cortex-A9多核處理器、L2緩存控制器和CoreSight跟蹤架構。工作電壓區間為 0.875 V ~ 1.30 V。 Cortex-A9的工作頻率區間為200 MHz ~ 1.4 GHz。CoreSight 時鐘的上限值為200MHZ。在CPU區中的時鐘管理單元 (CMU_CPU)生成在CPU塊中所有設備端口所需的時鐘頻率。Cortex_A9核心的頻率也是由它產生的。
2） DMC block consists of the DRAM memory controller (DMC), Security sub-system (SSS), and Generic Interrupt Controller (GIC). CMU in DMC block (CMU_DMC) generates 400 MHz DRAM clock, 200 MHz AXI bus clock which is synchronized with the DRAM clock, and 100MHz clock for register accesses. It also generates 200 MHz clock for Accelerator Coherency Port (ACP) bus, which is used for memory coherency checking and connects CPU and SSS bus masters.
DMC塊由DRAM存儲控制器（DMC）、安全子系統（SSS）和通用中斷控制器（GIC）組成。CMU在DMC塊（CMU_DMC）產生400MHZ的DRAM時鐘、200MHZ的用作同步DRAM的AXI總線時鐘 和 100MHZ的寄存器通道時鐘。它還為用來內存相干性檢查、連接cpu或安全子系統總線主控制器的總線，叫加速干預端口(ACP)總線，產生一個200MHZ的時鐘。
3）The LEFTBUS and RIGHTBUS blocks contain the global data buses that are clocked at 200 MHz. The global data buses transfer data between the DRAM and various sub-blocks. It also contains global peripheral buses that are clocked at 100 MHz. You can use 100 MHz clock for register accesses.
LEFTBUS和RIGHTBUS子塊包含一個時鐘為200MHZ的全局數據總線。全局數據總線在DRAM和各個子塊之間傳輸數據。它同樣包含時鐘為100MHZ的全局外圍總線。可以使用100MHZ的時鐘頻率在寄存器通道上。
4）CMU_TOP generates clocks for all the remaining function blocks, which include G3D, MFC, LCD0, ISP, CAM, TV, FSYS, MFC, GPS, MAUDIO, PERIL, and PERIR. It generates bus clocks that operate at 400 / 200 / 160 / 133 / 100 MHz. It also generates various special clocks to operate IPs in Exynos 4412 SCP.
CMU_TOP為所有剩下的子塊產生時鐘。剩下的子塊包括： G3D, MFC, LCD0, ISP, CAM, TV, FSYS, MFC, GPS, MAUDIO, PERIL, 和 PERIR。它產生總線時鐘工作在400/ 200/ 160/ 133/ 100MHZ。它同樣可以用來為Exynos4412的片上系統端口產生特殊的時鐘。
5）Additionally asynchronous bus bridges are inserted between two different function blocks.
還有，在不同的功能塊之間有一個異步總線橋。
7.2 Clock Declaration時鐘描述
The top-level clocks in Exynos 4412 SCP are:
> Clocks from clock pads, namely, XRTCXTI, XXTI, and XUSBXTI.
> Clocks from CMUs
For instance, ARMCLK, ACLK, HCLK, and SCLK
@ ARMCLK specifies clock for Cortex-A9 MPCore (up to 800 MHz @1.0 V, 1 GHz @ 1.1 V).
@ ACLK, HCLK, PCLK specify bus clocks.
@ SCLK (Special clock) specifies all clocks except bus clocks and processor core clock.
>Clocks from USB PHY
>Clocks from HDMI_PHY
>Clocks from GPIO pads
在Exynos4412片上系統中的頂層級別的時鐘都有：
1）來自時鐘墊的時鐘，如：XRTCXTI, XXTI, and XUSBXTI.
2）來自CMUs的時鐘：如，ARMCLK, ACLK, HCLK, and SCLK
@ ARMCLK規定了Cortex-A9多核處理器的時鐘；
@ ARMCLK, ACLK, HCLK, 和SCLK規定了總線時鐘；
@SCLK(特殊時鐘)規定了除了總線時鐘和處理器核心時鐘外的所有時鐘。
3）來自USB PHY的時鐘
4）來自HDMI_PHY的時鐘
5）來自GPIO根的時鐘
7.2.1 Clocks from Clock Pads
The clock pads derive the clocks. They are:
時鐘墊是時鐘的來源。他們是：
1) XRTCXTI: Specifies the clock generated from the crystal pad of 32.768 KHz with XRTCXTI and XRTCXTO pins. XRTCXTI and XRTCXTO are the two pins of crystal pad. RTC uses this clock as a source to the real-time clock. It requires a parallel resistance of 10 MΩ between the XUSBXTI and XUSBXTO pins.
1）XRTCXTI：說明了時鐘來自有 XRTCXTI 和 XRTCXTO管腳的32.768KHZ的水晶墊。 XRTCXTI 和 XRTCXTO是水晶墊的兩個管腳。RTC使用這樣的時鐘作為實時時間的時鐘。這需要在 XRTCXTI 和 XRTCXTO管腳之間安置平行 10 MΩ阻抗。
2) XXTI: Specifies the clock from external oscillator with XXTI pins. XXTI use wide-range OSC pads. When USB PHY is not used in commercial set, CMUs and phase-locked loops, namely, APLL, MPLL, VPLL, and EPLL use this clock as a supply source for appropriate modules. The input frequency of the clock ranges from 12 MHz to 50 MHz. When XXTI pin is not used, the pin should be tied to ground (GND). You can use the XXTI pin only for testing purpose.
2）XXTI：表明時鐘來自有XXTI引腳的外部震蕩器。XXTI使用寬范圍的OSC源。當USB PHY不使用商業模塊套件時，CMUs和鎖相環（又叫APLL,MPLL,和VPLL）使用這種時鐘來支持恰當的模塊。時鐘的輸入頻率為12MHZ到50MHZ之間。當XXTI管腳閑置不用是，應該接地。你只能使用XXTI管腳作為測試一用。
3) XUSBXTI: Specifies the clock from crystal pad with XUSBXTI and XUSBXTO pins. XUSBXTI and XUSBXTO use wide-range OSC pads. This clock is supplied to the USB PHY and the phase locked loops, namely, APLL, MPLL, VPLL, and EPLL. Refer to Chapter 36 USB HOST and Chapter 37 USB DEVICE, for more information. We recommend using a 24 MHz crystal as the iROM design is based on the 24 MHz input clock. It requires parallel resistance of 5MΩbetween the XUSBXTI and XUSBXTO pins.
3）XUSBXTI：表明時鐘來自接有XUSBXTI和XUSBXTO管腳的時鐘墊。XUSBXTI和XUSBXTO使用寬范圍的OSC源。這種時鐘支持USB PHY和鎖相環（又叫APLL/MPLL/VPLL和EPLL）。詳情請參考36章USB HOST和37章節USB DEVICE。我們推薦使用24MHZ水晶來設計iROM是建立在有24MHZ的輸入時鐘的基礎上的。它需要在 XUSBXTI和XUSBXTO管腳之間使用一個5MΩ的水平阻抗。
7.2.2 Clocks from CMU 來自CMU的時鐘
CMUs generate internal clocks with intermediate frequencies using from clocks from the clock pads. They are:
CMUs使用來自時鐘墊的時鐘，產生中等頻率的內部時鐘。使用的時鐘墊有：
1）Clock pads, namely, XRTCXTI, XXTI, and XUSBXTI
2）Four PLLs, namely, APLL, MPLL, EPLL, and VPLL
3）USB PHY and HDMI PHY
Some of these clocks are selected, pre-scaled, and provided to the corresponding modules. We recommend using 24 MHz input clock source for APLL, MPLL, EPLL, and VPLL. The components to generate internal clocks are:
其中有個時鐘被選中，接著預分頻，然后提供給通信模塊通信。我們推薦使用24MHZ提供給APLL/MPLL/EPLL/VPLL鎖相環作為輸入時鐘源。生成內部時鐘的組件有：
1）APLL uses FINPLL as input to generate frequencies from 22 to 1400 MHz.
2）MPLL uses FINPLL as input to generate frequencies from 22 to 1400 MHz.
3）EPLL uses FINPLL as input to generate frequencies from 22 to 1400 MHz. This PLL generates a 192 MHz clock for the Audio Sub-system. It pides EPLL output to generate 24 MHz SLIMbus clock.
4）VPLL uses FINPLL or SCLK_HDMI24M as input to generate frequencies from 22 to 1400 MHz. This PLL generates 54 MHz video clock or G3D clock.
5）USB Device PHY uses XUSBXTI to generate frequencies of 30 and 48 MHz.
6）HDMI PHY uses XUSBXTI to generate 54 MHz.
In typical Exynos 4412 SCP applications,
1）Cortex-A9 MPCore, CoreSight, and HPM use APLL.
2）DRAM, system bus clocks, and other peripheral clocks like audio IPs, and SPI use MPLL and EPLL.
3）Video clock uses VPLL.
4）G3D uses MPLL or VPLL as input clock source.
Clock controllers allow bypassing of PLLs for low frequency clock. They also provide clock gating to each block, thereby reducing power consumption.
在典型的Exynos 4412片上系統的應用中，
1）Cortex-A9多核處理器核心、CoreSight 和 HPM 使用 APLL.
2）DRAM、系統總線時鐘和其他的外圍時鐘（如 audio設備端口）和SPI使用MPLL和EPLL
3）視頻時鐘使用VPLL
4）G3D使用MPLL 或者 VPLL作為輸入時鐘源。
時鐘控制器允許使用PLLs來支持降頻，同時也支持為每個設備塊提供倍頻，以此來減輕電源消耗。
7.3 Clock Relationship
The clock relationship between various clocks are:
各個時鐘之間的關系有：
1） CPU_BLK clocks
@ freq (ARMCLK) = freq (MOUTCORE)/n, where n = 1 to 16
@ freq (ACLK_COREM0) = freq (ARMCLK)/n, where n = 1 to 8
@ freq (ACLK_COREM1) = freq (ARMCLK)/n, where n = 1 to 8
@ freq (PERIPHCLK) = freq (ARMCLK)/n, where n = 1 to 8
@ freq (ATCLK) = freq (MOUTCORE)/n, where n = 1 to 8
@ freq (PCLK_DBG) = freq (ATCLK)/n, where n = 1 to 8
2） DMC_BLK clocks
@ freq (SCLK_DMC) = freq (MOUTDMC_BUS)/n, where n = 1 to 8
@ freq (ACLK_DMCD) = freq (SCLK_DMC)/n, where n = 1 to 8
@ freq (ACLK_DMCP) = freq (ACLK_DMCD)/n, where n = 1 to 8
@ freq (ACLK_ACP) = freq (MOUTDMC_BUS)/n, where n = 1 to 8
@ freq (PCLK_ACP) = freq (ACLK_ACP)/n, where n = 1 to 8
@ freq (SCLK_C2C) = freq (MOUTC2C)/n, where n = 1 to 8
@ freq (ACLK_C2C) = freq (SCLK_C2C)/n, where n = 1 to 8
3）LEFTBUS_BLK clocks
@ freq (ACLK_GDL) = freq (MOUTGDL)/n, where n = 1 to 8
@ freq (ACLK_GPL) = freq (ACLK_GDL)/n, where n = 1 to 8
4）RIGHTBUS_BLK clocks
@ freq (ACLK_GDR) = freq (MOUTGDR)/n, where n = 1 to 8
@ freq (ACLK_GPR) = freq (ACLK_GDR)/n, where n = 1 to 8
5）CMU_TOP clocks
@ freq (ACLK_400_MCUISP = freq (MOUTACLK_400_mcuisp)/n, where n = 1 to 8
@ freq (ACLK_200) = freq (MOUTACLK_200)/n, where n = 1 to 8
@ freq (ACLK_100) = freq (MOUTACLK_100)/n, where n = 1 to 16
@ freq (ACLK_160) = freq (MOUTACLK_160)/n, where n = 1 to 8
@ freq (ACLK_133) = freq (MOUTACLK_133)/n, where n = 1 to 8
@ freq (SCLK_ONENAND) = freq (MOUTONENAND)/n, where n = 1 to 8
6）MAUDIO_BLK clocks
@ freq (RP_CLK) = freq (MOUTASS)/n, where n = 1 to 16
@ freq (BUS_CLK) = freq (MOUTRP)/n, where n = 1 to 16
Caution: Ensure that the ratio between the SCLK_DMC and ACLK_DMCD frequency should be 2:1 or 1:1
always. Do not change this ratio during the running state of DMC. You should also ensure that the
ratio between the SCLK_C2C and ACLK_C2C frequency should be 2:1. You should not change this
ratio during the running state of C2C.
警告：確保SCLK_DMC:ACLK_DMCD = 2:1或者1:1；不能在DMC運行狀態的時候改變這個比率。同時應該確保SCLK_C2C：ACLK_C2C = 2:1；不能在C2C運行狀態是改變該值。
The values for high-performance operation are:
高性能操作使用值如下：
• freq (ARMCLK) = 1400 MHz at 1.3 V
• freq (ACLK_COREM0) = 350 MHz at 1.3V
• freq (ACLK_COREM1) = 188 MHz at 1.3 V
• freq (PERIPHCLK) = 1400 MHz at 1.3 V
• freq (ATCLK) = 214 MHz at 1.3 V
• freq (PCLK_DBG) = 107 MHz at 1.3 V
• freq (SCLK_DMC) = 400 MHz at 1.0 V
• freq (ACLK_DMCD) = 200 MHz at 1.0 V
• freq (ACLK_DMCP) = 100 MHz at 1.0 V
• freq (ACLK_ACP) = 200 MHz at 1.0 V
• freq (PCLK_ACP) = 100 MHz at 1.0 V
• freq (SCLK_C2C) = 400 MHz at 1.0 V
• freq (ACLK_C2C) = 200 MHz at 1.0 V
• freq (ACLK_GDL) = 200 MHz at 1.0 V
• freq (ACLK_GPL) = 100 MHz at 1.0 V
• freq (ACLK_GDR) = 200 MHz at 1.0 V
• freq (ACLK_GPR) = 100 MHz at 1.0 V
• freq (ACLK_400_MCUISP) = 400 MHz at 1.0 V
• freq (ACLK_200) = 160 MHz at 1.0 V
• freq (ACLK_100) = 100 MHz at 1.0 V
• freq (ACLK_160) = 160 MHz at 1.0 V
• freq (ACLK_133) = 133 MHz at 1.0 V
• freq (SCLK_ONENAND) = 160 MHz at 1.0 V
The PLL operations are:
1） APLL mainly drives the CPU_BLK clocks. It generates frequencies up to 1.4 GHz with a duty ratio of 49:51.
APLL also generates DMC_BLK, LEFTBUS_BLK, RIGHTBUS_BLK, and CMU_TOP clocks as supplement of
MPLL.
2）MPLL mainly drives the DMC_BLK, LEFTBUS_BLK, RIGHTBUS_BLK, and CMU_TOP clocks. It generates
frequencies up to 1 GHz with a duty ratio of 49:51. MPLL also generates CPU_BLK clocks when it blocks
APLL for locking during the Dynamic Voltage Frequency Scaling (DVFS).
3）EPLL mainly generates an audio clock.
4）VPLL mainly generates video system operating clock of 54 MHz, or a G3D clock, or 440 MHz clock at 1.1 V.
鎖相環的用法：
1）APLL主要用來驅動CPU_BLK時鐘。當占空比為49:51時，能產生一個高頻率1.4GHZ。APLL也能產生DMC_BLK/ LEFTBUS_BLK/ RIGHTBUS/ CMU_TOP時鐘，用來給MPLL提供驅動支持。
2）MPLL主要驅動DMC_BLK/ LEFTBUS_BLK/ RIGHTBUS_BLK/ CMU_TOP時鐘。占空比為49:51時，MPLL能產生一個高頻率1GHZ。當MPLL用來阻塞APLL在動態電壓掃描（DVFS）時的鎖定時，MPLL也產生CPU_BLK時鐘。
3）EPLL主要用來產生一個音頻時鐘。
4）VPLL主要用來產生一個54MHZ的視頻系統操作時鐘，或者一個G3D時鐘，或者一個在1.1V電壓下的440MHZ時鐘。
7.3.3 Recommended PLL PMS Value for VPLL
Table 7-4 describes the recommended PLL PMS value for VPLL.
表7-4描述了推薦的VPLL對應的PLL計劃維護體系值。
NOTE:
1. Although there is an equation for choosing PMS values, we strongly recommend only the values in the above table.
If you have to use other values, please contact us.
2. K value description "Positive value (Negative value)": Positive values is that you should write to EPLLCON/VPLLCON register. Negative value is that you can calculate PLL output frequency with it.
注意：
1. 盡管有選擇PMS值的計算方程等式。但是我們強烈推薦僅使用以上表格中的值。如果你必須使用表格以外的值，請聯系三星公司。
2. K 值描述了正負值：正值要寫到EPLLCON或者VPLLCON寄存器。負值你可以用它來乘以PLL的輸出值。
7.4 Clock Generation時鐘的產生
Figure 7-2 and Figure 7-3, illustrates the block diagram of the clock generation logic. The clock generator consists of an external crystal clock that is connected to the oscillation amplifier. The PLL converts the incoming low frequency to a high frequency clock that is required by the Exynos 4412 SCP. The clock generator also includes a built-in logic to stabilize the clock frequency for each system reset. The clock requires a specified time for stabilization.
圖7-2和圖7-3，插圖說明了時鐘產生邏輯的區域表。時鐘發生器由一個連接到震蕩放大器上的外部晶振組成。鎖相環PLL把接收到的低頻轉化為Exynos4412片上系統所需的高頻。時鐘生成器同樣也需要一個內嵌的邏輯單元來為每次重置系統建立穩定的時鐘頻率。時鐘需要一段特定的時間來穩定下來。
Figure 7-2 and Figure 7-3 illustrates the two types of clock MUX. Clock MUX in grey color represents glitch-free clock MUX that is free of glitches while changing the clock selection. Clock MUX in white color represents non- glitch-free clock MUX that can suffer from glitches while changing the clock sources. You have to be careful while using each clock MUX.
圖7-2和圖7-3，插圖說明了兩種類型的時鐘復用器(MUX)。灰色的時鐘復用器表示一種無干擾的時鐘復用器，也就是在改變時鐘選區時不受干擾。白色的時鐘復用器表示有干擾的時鐘復用器，也就是說在改變時鐘源時，要遭受脈沖信號。要小心使用任何一個時鐘復用器。
For glitch-free MUX, you should ensure that all clock sources are running while changing the clock selection. If not, it implies that the clock selection process is not complete and it results in clock output having unknown states. The clock MUX status registers are identified with a keyword that starts with CLK_MUX_STAT
對于無干擾性的復用器，你需要在改變時鐘選區時確保每一個時鐘源都在工作。如果不能保證，這就表明了選擇時鐘的過程并沒有完成，會導致未知的時鐘輸出狀態。時鐘復用器的狀態計算器被認定為CLK_MUX_STAT開始。
For non-glitch-free clock MUX, glitches may occur while changing the clock selection. To prevent glitch signals, we recommend disabling the output of a non-glitch-free MUX before any change of clock selection. After completing the clock change, you can re-enable the output of the non-glitch-free clock MUX. This is done to ensure that there are no glitches resulting due to the clock change selection. The outputs of non-glitch-free MUXES are masked by the clock source mask control registers. The clock source mask control registers are identified with a keyword that starts with CLK_SRC_MASK.
對于有干擾性時鐘復用器，在改變時鐘選區的時候可能有脈沖信號的產生。為了避免有脈沖信號的影響，我們建議在時鐘選區改好之前，先關閉這種復用器的輸出功能。在完成選區的更換后，你可以重新使能復用的輸出功能。有干擾型的時鐘復用器的輸出功能"MUXES"在時鐘源屏蔽控制寄存器中可被屏蔽。時鐘源屏蔽控制寄存器以“CLK_SRC_MASK”關鍵字開頭標識。
Figure 7-2 and Figure 7-3 illustrates a clock pider that indicates possible piding value in parentheses. The piding values can be changed by clock pider registers during run-time. Some clock piders have only one piding value and you are not allowed to change the piding value.
圖7-2和圖7-3，插圖說明了一個時鐘分頻器，可以從其輸入源來對時鐘分頻。在運行態，分頻值可以通過修改時鐘分頻寄存器來修改。但是有一些時鐘分頻器只有一種分頻值，其分頻值不允許被修改。
Figure 7-2 illustrates the Exynos 4412 SCP Clock Generation Circuit (CPU, BUS, DRAM, and ISP Clocks) diagram.
圖7-2插圖說明了Exynos4412片上系統時鐘生成電路（CPU/BUS/DRAM/ ISP時鐘）表。
Figure 7-3 illustrates the Exynos 4412 SCP Clock Generation Circuit (Special Clocks) diagram.
圖7-3插圖說明了Exynos4412片上系統的時鐘生成電路（特殊時鐘）表
